1. Technical Field
The present invention relates generally to synchronous, dynamic random access memories (xe2x80x9cSDRAMsxe2x80x9d), and, in particular, to double data rate (xe2x80x9cDDRxe2x80x9d) SDRAMs.
2. Background Art
In general, in the descriptions that follow, we will italicize the first occurrence of each special term of art which should be familiar to those skilled in the art of DRAMs, and, in particular, DDR DRAMs. In addition, when we first introduce a term that we believe to be new or that we will use in a context that we believe to be new, we will bold the term and provide the definition that we intend to apply to that term. From time to time, throughout this description, we will use the terms assert and negate when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively. We may also use the term High-Z to refer to a signal that is allowed to float between the power rails, with or without external termination to provide an appropriate bias voltage. Furthermore, although we may refer to the electrical interface structures of integrated circuit devices or chips as pins, we recognize that other chip packaging technologies may employ equivalent, alternative structures, such as solder balls (in ball grid arrays and the like), or wire bonds (for multi-chip modules and the like). Likewise, although we may refer to the chip mounting structure as a printed circuit board (xe2x80x9cPCBxe2x80x9d), we recognize that other multi-chip mounting technologies may employ equivalent, alternative structures, such as flexible substrates or, again, multi-chip modules. Accordingly, unless we expressly indicate to the contrary, we will use such terms generically, intending those terms to encompass all such current and future equivalent technologies.
The JEDEC Solid State Technology Association (xe2x80x9cJEDECxe2x80x9d) is the semiconductor engineering standardization body of the Electronic Industries Alliance (xe2x80x9cEIAxe2x80x9d). Among the many standards specified by JEDEC is one for DDR SDRAMs (the xe2x80x9cStandardxe2x80x9d). In general, the Standard defines the signaling protocol for the exchange of data between a memory controller and a DDR SDRAM. During each such exchange, the device that is attempting to transmit data (the xe2x80x9ctransmitterxe2x80x9d) is required to transmit, along with the data itself, a data strobe (xe2x80x9cDQSxe2x80x9d) to facilitate the capture of that data by the device that is attempting to receive the data (the xe2x80x9creceiverxe2x80x9d). According to the Standard, from the perspective of the DDR SDRAM, input (i.e., xe2x80x9cWRITExe2x80x9d) data is registered on both edges of DQS and output (i.e., xe2x80x9cREADxe2x80x9d) data is referenced to both edges of DQS. For example, during a WRITE operation, the memory controller is the transmitter and must transmit the DQS strobe to the DDR SDRAM so as to be center-aligned with the data. In contrast, during a READ operation, the DDR SDRAM is the transmitter and must transmit the DQS strobe to the memory controller so as to be edge-aligned with the data. Thus, it is the responsibility of the memory controller to generate DQS for all WRITEs and to recover DQS for all READs, while it is the responsibility of the DDR SDRAM to generate DQS for all READs and to recover DQS for all WRITEs.
The Standard further specifies the use of SSTLxe2x80x942 Class I/II compatible signaling (as specified in another JEDEC standard). As is commonly known, SSTLxe2x80x942 signaling requires some form of external termination to bias external input/output signals (xe2x80x9cI/Osxe2x80x9d) to the system reference voltage (xe2x80x9cVrefxe2x80x9d) of 1.25 Volts. Inherent in the use of such a relatively low reference voltage is reduced noise immunity. While it is certainly possible to design a DDR SDRAM system which will perform reliably for these conditions, it is often the case that tradeoffs are made for cost or other reasons that tend to have adverse effects in terms of system noise performance.
Since the primary function of the DQS signal is as control strobe for data transfer transactions, the Standard specifies that DQS, when not in use, may be allowed to go High-Z. Since it is possible, when in this state, for DQS to experience spurious, noise-induced transitions towards one or the other of the power rails, the Standard requires the transmitter to prepend a preamble to the initial assertion of DQS of a transfer operation, during which time DQS is negated. Thus, for example, for a burst transfer operation, the preamble must be provided for only the first assertion of DQS, but not for the subsequent assertions in the burst. Similarly, to prepare DQS for going High-Z at the end of a transfer operation, the transmitter is required to append a postamble, during which time DQS is again negated.
In normal operation, the memory controller can initiate a READ operation by issuing to the DDR SDRAM a READ command. In response, the DDR SDRAM will retrieve a predetermined portion of the data stored therein beginning at the particular address specified in the READ command. When ready to transmit the retrieved data, the DDR SDRAM will first generate the DQS preamble, then transmit the data, edge-aligned with both the rising and falling edges of DQS, and, finally, generate the DQS postamble. This sequence, however, is a bit problematic from the point of view of the memory controller: if, after issuing the READ command and before the DDR SDRAM generates the DQS preamble, a noise glitch occurs on DQS, first driving it low then driving it high, it is possible for the memory controller to mistakenly interpret the glitch as the real DQS, and thus react prematurely and capture garbage (and, concomitantly, miss the actual data). Notwithstanding the care taken by JEDEC to address system issues such as this, we submit that this particular problem will become increasingly more intractable as system clock rates rise in subsequent generations of DDR devices. Given the inherent difficulty in coordinating two electronic circuits physically located on separate chips, e.g., the DDR SDRAM and the memory controller, there may be no completely satisfactory solution for such inter-chip transactions, short of using the sophisticated mixed-signal clock forwarding/recovery techniques common in high-speed telecommunication devices. We submit that, at least until the operating speeds of DDR SDRAMs absolutely require such exotic (and expensive) technology, a simpler, less expensive solution is needed for improving the noise immunity of systems having DDR SDRAMs.